A) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a contact etch stopper film having stress therein and formed above a semiconductor substrate.
B) Description of the Related Art
There are high demands for high integration and high speed of semiconductor integrated circuit devices. High integration and high speed have been achieved conventionally by reducing the size of a MOS field effect transistor (FET) which is a main constituent element of a semiconductor integrated circuit device. Miniaturization can obviously improve the integration degree and a shortened gate length can increase an operation speed. Miniaturization has been supported by lithography technologies of transferring a design pattern to a resist film. The requested minimum patterning size has become recently a size smaller than the wavelength of light used by lithography, and further miniaturization of MOSFETs is becoming difficult.
A field effect transistor using a silicon oxide film on a semiconductor substrate as the gate insulating film (even by using not metal but semiconductor silicon as the gate electrode) has been called a MOSFET. As FETs are made fine, some structures have been adopted such as the structure that a silicon oxynitride film is used as the gate insulating film and the structure that a high dielectric constant insulating film of HfO2 or the like stacked on a silicon oxide film is used as the gate insulating film. In this specification, FET having a gate insulating film made of insulators other than silicon oxide is also called MOSFET.
Namely, MOSFET is intended to mean a semiconductor field effect transistor having an insulated gate electrode.
Most of semiconductor integrated circuit devices aiming at low power consumption use a complementary (C) MOSFET (abbreviated to CMOS) constituted of an n-channel MOSFET (n-MOSFET) and a p-channel MOSFET (p-MOSFET). In order to realize high speed of a CMOS integrated circuit, it is desired to improve the performance of both n-MOSFET and p-MOSFET.
A non-patent document No. 1 “IEDM 2000 Tech. Dig., p. 247” by Ito et al reports that as a compressive stress in a contact etch stopper film is made large, which film is a silicon nitride film formed by plasma-enhanced (PE) chemical vapor deposition (CVD) and a compressive stress film, a compressive stress is exerted along a gate length direction so that an on-current of p-MOS increases and an on-current of n-MOS decreases.
A non-patent document No. 2 “IEDM 2000 Tech. Dig., p. 575” by Ootsuka et al reports that as a tensile stress in a contact etch stopper film is made large, which film is a silicon nitride film formed by thermal CVD and a tensile stress film, a tensile stress is exerted along a gate length direction so that an on-current of n-MOS increases and an on-current of p-MOS decreases.
The compressive stress film is a film formed on an underlying silicon substrate in a compressed state. The compressive stress film has a compressive stress therein. The tensile stress film is a film formed on an underlying substrate in a stretched state. The tensile stress film has a tensile stress therein.
As described above, as the inner stress of a contact etch stopper film is increased, the on-current increases in one of an n-MOSFET and a p-MOSFET and decreases in the other so that the increase and decrease are canceled out and there is the tendency that the performance of the whole CMOS cannot be improved.
A non-patent document No. 3 “IEDM 2001 Tech. Dig., p. 433” by Shimizu et al reports that a silicon nitride film having a strong stress therein is used as a contact etch stopper film and Ge ions are implanted into a MOSFET region of a conductivity type of reducing an on-current to release the stress. If the contact etch stopper film is made of a silicon nitride film having a strong compressive stress formed by PE-CVD, Ge ions are implanted in the n-MOS region. If the contact etch stopper film is made of a silicon nitride film having a strong tensile stress formed by thermal CVD, Ge ions are implanted in the p-MOS region. It is possible to suppress a reduction in the on-current of MOSFET whose performance is otherwise degraded and to improve the performance of the whole CMOS.
A non-patent document No. 4 “SSDM 2002, p. 14” by Kumagai et al and a patent document No. 1, Japanese Patent Publication No. 2003-86708, disclose that if the gate length direction is disposed along the <110> direction on an Si (001) plane, the on-current of n-MOS increases by the tensile stress along the gate length direction and decreases by the tensile stress along a gate width direction, whereas the on-current of p-MOS decreases by the tensile stress along the gate length direction (increases by the compressive stress along the gate length direction) and decreases by the tensile stress along the gate width direction.
The patent document No. 1, Japanese Patent Publication No. 2003-86708, further discloses that a contact etch stopper film is made of a tensile stress film and disposed in an n-MOS region, and a contact etch stopper film is made of a compressive stress film and disposed in a p-MOS region, to improve the performance of the whole CMOS and to adjust the stress by the area of each contact etch stopper film.
A patent document No. 2, Japanese Patent Publication No. 2003-273240, discloses that in the state that the semiconductor surface between a gate insulating film and an element isolation region is covered with an insulating film functioning as a contact etch stopper film, a tensile stress film is formed in an n-MOS region and a compressive stress film is formed in a p-MOS region.